X. Miao, Ruqiang Bao, et al.
IEEE Electron Device Letters
III-V semiconductors, especially InAs, have much higher electron mobilities than Si and have been considered as promising candidates for n-channel materials for post-Si low-power CMOS logic applications. Combined with the inherent 3-D structure that enables the gate-all-around (GAA) geometry for superb gate electrostatic control, III-V nanowire (NW) MOS-FETs are well positioned to extend the scaling beyond Si. This paper attempts to provide a review of the growth and fabrication approaches (both bottom-up and top-down), and the state-of-the-art device performance of III-V NW GAA MOSFETs, as well as an outlook of their scaling potential.
X. Miao, Ruqiang Bao, et al.
IEEE Electron Device Letters
Hiroaki Niimi, Zuoguang Liu, et al.
IEEE Electron Device Letters
Zuoguang Liu, Heng Wu, et al.
VLSI Technology 2019
Oleg Gluschenkov, Zuoguang Liu, et al.
IEDM 2016