Yasunao Katayama, Yasushi Negishi, et al.
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
We present new complementary logic circuits that exploit an intrinsic bistability in nano-scale coupled quantum wells. When operated with a multiple-phase split-level clocking scheme, the device can latch a binary digit while meeting gain, tolerance, and I/O decoupling requirements at the same time, which were difficult with conventional back-to-back negative differential resistance devices. This same structure can function as a complete set of classical complementary logic circuits as well, by changing only the connections of the input signals. When these circuits are cascaded, efficient charge recycling can be achieved. ©2004 ieee.
Yasunao Katayama, Yasushi Negishi, et al.
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Atsuya Okazaki, Yasunao Katayama, et al.
CF 2011
Toshiaki Kirihata, Sang H. Dhong, et al.
IEEE Journal of Solid-State Circuits
Yasunao Katayama
IEEE Micro