Yasunao Katayama, Yasushi Negishi, et al.
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Recently, we proposed new complementary logic circuits using nano-scale coupled quantum wells [12]. In this paper, we explore a systematic way of modeling the device at physical and circuit levels for nano-scale coupled open quantum systems. The physical interface between coupled and uncoupled regions is considered as a junction where electrons can be coherently injected. The circuit model treats the system as a multimode ID system with virtually separated nodes assigned for the chemical and static potentials. The model explains simulated tunneling lineshapes well. ©2005 IEEE.
Yasunao Katayama, Yasushi Negishi, et al.
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Atsuya Okazaki, Yasunao Katayama, et al.
CF 2011
Toshiaki Kirihata, Sang H. Dhong, et al.
IEEE Journal of Solid-State Circuits
Yasunao Katayama
IEEE Micro