Current focus is research and development for scaling up future IBM Quantum Computing Systems.
(1) Improving key Quantum metrics: qubit coherence time, readout fidelity, single and two qubit gate error in order to achieve 2X-fold increased Quantum volume per year.
(2) Cryogenic (sub 100mK) measurements of superconductor-based qubits in the microwave frequency regime.
(3) Improving System stability by variability mitigation in order to enable accurate simulation output for our clients.
Past Experience in CMOS device technology, academia and education:
(1) Semiconductor technologist with ~ 15 years experience in leading-edge CMOS device engineering.
(2) Successful delivery to product of high performance CMOS SOI technology logic nodes: 65-nm, 45-nm, 32-nm, and 22-nm and 14-nm (FINFET on SOI) for IBM high performance servers working with the SRDC development team.
(3) Recent focus was working to enable 7nm (LP- leading performance) technology.
(4) Skills: CMOS device design, device physics, high frequency R.O. circuit layout, characterization, process health/yield, diagnostic test setup, Power/performance benchmarking including automation, DOE, Technology element definition, clean room fabrication, PDK-based targeting, Identification of variability sources in advanced technologies & defining countermeasures. Process Integration (novel materials), test structure design, TCAD calibration, transport physics, quantum effects, digital logic design, probe testing/characterization of semiconductor devices.
(5) Academic experience working as an Associate Professor at Masdar Institute of Science and Technology established in cooperation with MIT.
(6) Education: Received Ph.D. (2003) in Electrical Engineering in the area of strained silicon devices from MIT (Cambridge, Massachusetts).
(7) Authored or co-authored 32 technical publications and 9 patents and is a senior member of the IEEE.