A Multiscale Workflow for Thermal Analysis of 3DI Chip Stacks
Max Bloomfield, Amogh Wasti, et al.
ITherm 2025
It is challenging to successfully bond large Si chips onto a package substrate with fine-pitch solder bumps. Relatively large pad coplanarity of a package substrate causes open joints or solder bridges. We propose a new solder deposition approach that controls solder volume on each pad, aiming to achieve a 40 µ m pitch joining of a large Si chip with a chip size of 29 x 12 mm onto a package substrate. In the new approach, the thickness of the resist mask is locally modified in addition to the resist opening width. This allows a wider range of solder volume to be deposited on individual pads, thereby compensating for larger pad coplanarity. In this study, we measured the surface profile of package substrates under various conditions. Then, we investigated the effect of pad density and exposure dose on resist thickness and examined whether the combination of the variable resist thickness and variable opening diameter could compensate for the surface topography of package substrates. We also report solder deposition results.
Max Bloomfield, Amogh Wasti, et al.
ITherm 2025
Jean Benoit Héroux, Tomofumi Kise, et al.
Journal of Lightwave Technology
Xiaofan Zhang, Haoming Lu, et al.
MLSys 2020
Victor Chan, A. Gasasira, et al.
IEEE Trans Semicond Manuf